The continuing trend of scaling down integrated circuits has forced the semiconductor industry to consider new techniques for fabricating precise components at sub-micron levels. Along with the need for smaller components, there has been a growing demand for devices requiring less power consumption. In the manufacture of memory devices, these trends have led the industry to refine approaches to achieve thinner capacitor cell dielectric and surface enhanced storage capacitor electrodes.
As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. In semiconductor devices it may be advantageous to build contact plugs for interlayer connections with high aspect ratio structures as circuit density will be enhanced. Also, in dynamic random access memory (DRAM) devices it is essential that storage node capacitor cell plates be large enough to exhibit sufficient capacitance in order to retain an adequate charge in spite of parasitic capacitance and noise that may be present during circuit operation. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices. The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
The present invention develops a method to form high aspect ratio structures, such as interconnecting contact plugs and storage capacitors. Greater circuit density will be possible as the fabricated device will benefit from deep contact plug interconnects and/or increased storage electrode surface areas than are attainable in conventional processing methods.